Computational Modeling and Simulation of Reconfigurable Responsive Embedded Computing Systems

Many computer applications required as solution provider inside larger, in general, complex systems. Hence these computer systems are embedded within the real complex systems, which themselves may consist of mechanical, electrical and/or electronical components etc. This led to the well-known terms of embedded systems, and often emdedded processors or embedded control. Embedded systems, as well as embedded control, with high reliability and hard realtime constraints, are the top end of embedded systems design, called embedded responsive systems. With the growing demands in this field, solutions are requested integrating operating systems, realtime capabilities as well as fault tolerance within a overall system approach. Due to those facts the term responisble system was introduced for such type of complex and configurable architectures. The most important features of responsive systems deal with reliability and realtime capability. Reliability as well as hard realtime capability demand both for intelligent scheduling algorithms. Scheduling means, that even in the sequentialized world of the processor concurrent requests may be served. Normally this is performed by static or dynamic scheduling algorithms with well-known advantages and disadvantages and checked by simulation methods. But intelligent scheduling is nothing else as scheduling per se because looking for the best priority schedule of the tasks in progress. Hence the hardcore boundary for responsive systems cannot be solved by the scheduling schemes known up to now. The other aspect is that the embedded controller as well as the embedded processor architecture inside shows no difference at all in compa-rison to ‘normal’ architectures. This paper introduces a block oriented structure for em-bedded controller as well as embedded processors in the area of responsive systems. This architecture will include computing capabilities for high performance tasks as well as hardware support for scheduling, and this yields to the need of simulation for system design and evaluation. Even fault tolerance – partial as well as global – is possible done based on simulation within the embedded controller architecture. This support should be introduced as hard-ware/software partitioning based on an extended block-oriented microarchitecture model for the embedded con-troller design in responsive systems. The demands for the simulation method change from separated hardware, operating system and application software simulation to integrated system co-simulation methods due to the mutual dependance of all system parts. Using system modelling languages like VHDL for the block oriented FPLD architecture it could be shown that some of the simulation results are obtainable by abstraction but some not. Field Programmable Logic De-vices (FPLDs) like Field Programmable Gate Arrays (FPGAs) have emerged as an ultimate solution to the time-to-market and risk problems in embedded controller design because they provide instant manufacturing and low-cost prototyping e.g. of embedded processor kernels, using simulation as a powerful design tool. An FPLD is a device in which the final logic structure can be directly configurated by the end user, without the use of an inte-grated circuit fabrication facility, because the user only needs some simple electrical equipment for programming purposes. First type of programmable logic device introduced into the market was the Programmable Read Only Memory (PROM), a one-time programmable device that consists of an array of read-only cells. Later these cells were as-sembled in EPROM or EEPROM technology enabling the re-programmability. A specific logic circuit can be imple-mented by using the PROM’s address lines as the circuit’s inputs, and the circuit’s outputs are then defined by the stored binary information. Based on this strategy, any binary function